The circuit structure of A/D converter includes successive approximation, integral, full parallel (flash), subranging, pipeline and Δ-Σ over-sampling. The main structure for high speed and high resolution A/D converter is the pipeline structure.
The concept of pipeline structure was introduced in 1987 by S. H. Lewis, et al, in which, lower resolution A/D converters was pipelined to realize a high resolution A/D converter. Based on the pipeline A/D converter, B. Ginetti, et al. introduced, in 1990, the theory of redundancy bit to realize a 1.5-bit/stage pipeline structure, which is widely used at present. In this structure, each pipelined stage has 1 significant bit and 1 redundancy bit, and each stage outputs one of three (00, 01, 10) codes. The output of all substages are properly delayed, and then sent to code reconstruction circuit for addition of overlapped bits, to generate the corrected output code. The structure corrects comparator offset errors by using redundancy bit and digital correction circuit, which is widely used in pipeline A/D converters. However, when used for high speed and high resolution A/D converters, this structure and the related digital correction method presented some problems: 1) the output voltage range of each substage occupies the full range of reference voltage [Vref−, Vref+], leaving no spare reference voltage range for introducing negative and positive redundancy bit codes; so, when input signal is smaller than Vref−, the output is all 0; and when input signal is greater than Vref+, the output is all 1. That is to say, the corrected output code can not identify the negative or positive overflow of the input signal; 2) the number of pipeline stages equals to A/D converter bits minus one. The more bits the converter has, the more pipeline stages there will be. Take 16-bit A/D converter as an example, when the pipeline structure of 1.5-bit/stage is used, then 15 pipeline stages will be needed, which greatly increases layout area and power consumption, compared to 8- and lower-bit A/D converter with the same structure; 3) the input/output delay time, which is directly proportional to the number of pipeline stages, increases with increasing stages.
As for the conventional digital correction method for comparator offset error, the structure of (n+0.5)-bit per stage is derived from the theory of 1.5-bit per stage, i.e. each pipeline stage inputs n bits of effective data and 1 redundancy, and outputs corresponding binary codes ranging from 0 to (2n+1−1). And the output of each stage is sent to code reconstruction circuit for addition of overlapped bits after a reasonable delay. When the conventional method is applied to digital correction of high speed and high resolution A/D converter, there exists the same problem, i.e. this method does not introduce negative and positive redundancy codes, so, it cannot identify underflow or overflow of the input signal.
Therefore, the existing conventional correction method need improving. It is essential to introduce negative and positive redundancy codes to identify underflow and overflow of input signals, while the number of stages is reduced.